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| IRFF120 Data Sheet March 1999 File Number 1563.3 6.0A, 100V, 0.300 Ohm, N-Channel Power MOSFET This N-Channel enhancement mode silicon gate power field effect transistor is an advanced power MOSFET designed, tested, and guaranteed to withstand a specified level of energy in the breakdown avalanche mode of operation. All of these power MOSFETs are designed for applications such as switching regulators, switching convertors, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. These types can be operated directly from integrated circuits. Formerly developmental type TA09594. Features * 6.0A, 100V * rDS(ON) = 0.300 * Single Pulse Avalanche Energy Rated * SOA is Power Dissipation Limited * Nanosecond Switching Speeds * Linear Transfer Characteristics * High Input Impedance * Related Literature - TB334, "Guidelines for Soldering Surface Mount Components to PC Boards" Ordering Information PART NUMBER IRFF120 PACKAGE TO-205AF BRAND IRFF120 Symbol D NOTE: When ordering, use the entire part number. G S Packaging JEDEC TO-205AF DRAIN (CASE) SOURCE GATE 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999 IRFF120 Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified IRFF120 100 100 6.0 24 20 20 0.16 36 -55 to 150 300 260 UNITS V V A A V W W/oC mJ oC oC oC Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Pulse Avalanche Energy Rating (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 125oC. TC = 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) IDSS ID(ON) IGSS rDS(ON) gfs td(ON) tr td(OFF) tf Qg(TOT) Qgs Qgd CISS COSS CRSS LD Measured from the Drain Lead, 5.0mm (0.2in) from Header to Center of Die Measured from the Source Lead, 5.0mm (0.2in) from Header to Source Bonding Pad Modified MOSFET Symbol Showing the Internal Devices Inductances D LD G LS S Electrical Specifications PARAMETER TEST CONDITIONS ID = 250A, VGS = 0V (Figure 10) VGS = VDS , ID = 250A VDS = Rated BVDSS , VGS = 0V VDS = 0.8 x Rated BVDSS , VGS = 0V, TC = 125oC VDS > ID(ON) x rDS(ON)MAX, VGS = 10V VGS = 20V ID = 3.0A, VGS = 10V (Figures 8, 9) VDS > ID(ON) x rDS(ON)MAX, ID = 3.0A (Figure 12) VDD 0.5 x Rated BVDSS, ID = 6.0A, RG = 9.1, VGS =10V (Figures 17, 18), RL = 8 for VDSS = 50V, RL = 6.3 for VDSS = 40V, MOSFET Switching Times are Essentially Independent of Operating Temperatures VGS = 10V, ID = 6.0A, VDS = 0.8 x Rated BVDSS (Figures 14, 19, 20) Gate Charge is Essentially Independent of Operating Temperature MIN 100 2.0 6.0 1.5 - TYP 0.25 2.9 20 37 50 35 10 6.0 4.0 450 20 50 5.0 MAX 4.0 25 250 100 0.300 40 70 100 70 15 - UNITS V V A A A nA S ns ns ns ns nC nC nC pF pF pF nH Drain to Source Breakdown Voltage Gate Threshold Voltage Zero Gate Voltage Drain Current On-State Drain Current (Note 2) Gate to Source Leakage Current Drain to Source On Resistance (Note 2) Forward Transconductance (Note 2) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Total Gate Charge (Gate to Source + Gate to Drain) Gate to Source Charge Gate to Drain ("Miller") Charge Input Capacitance Output Capacitance Reverse Transfer Capacitance Internal Drain Inductance VDS = 25V, VGS = 0V, f = 1MHz (Figure 11) - Internal Source Inductance LS - 15 - nH Thermal Resistance, Junction to Case Thermal Resistance, Junction to Ambient RJC RJA Free Air Operation - - 6.25 175 oC/W oC/W 2 IRFF120 Source to Drain Diode Specifications PARAMETER Continuous Source to Drain Current Pulse Source to Drain Current (Note 3) SYMBOL ISD ISM TEST CONDITIONS Modified MOSFET Symbol Showing the Integral Reverse P-N Junction Rectifier G D MIN - TYP - MAX 6.0 24 UNITS A A S Source to Drain Diode Voltage (Note 2) Reverse Recovery Time Reverse Recovery Charge Forward Turn-On Time NOTES: VSD trr QRR tON TJ = 25oC, ISD = 6.0A, VGS = 0V (Figure 13) TJ = 150oC, ISD = 6.0A, dISD/dt = 100A/s TJ = 150oC, ISD = 6.0A, dISD/dt = 100A/s Intrinsic Turn-on Time is Negligible, Turn-On Speed is Substantially controlled by LS + LD - 230 1.0 - 2.5 - V ns C - 2. Pulse test: pulse width 300s, duty cycle 2%. 3. Repetitive rating: pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure 3). 4. VDD = 25V, starting TJ = 25oC, L = 1.5mH, RG = 25, peak IAS = 6.0A (Figures 15, 16). Typical Performance Curves 1.2 POWER DISSIPATION MULTIPLIER 1.0 Unless Otherwise Specified 6.0 0.8 0.6 0.4 0.2 0 ID , DRAIN CURRENT (A) 4.8 3.6 2.4 1.2 0 50 100 150 0 25 50 75 100 125 150 TC , CASE TEMPERATURE (oC) TC , CASE TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE 1.0 ZJC, NORMALIZED THERMAL IMPEDANCE 0.5 0.2 PDM 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE 10-4 10-3 10-2 10-1 t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC x RJC + TC 1 10 0.01 10-5 t1, RECTANGULAR PULSE DURATION (s) FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE 3 IRFF120 Typical Performance Curves 50.0 10s ID, DRAIN CURRENT (A) 10.0 100s ID, DRAIN CURRENT (A) 16 VGS = 8V 12 VGS = 7V 8 VGS = 6V 4 DC TJ = MAX RATED 0.1 1.0 10.0 100.0 200.0 0 0 10 20 30 40 VDS, DRAIN TO SOURCE VOLTAGE (V) VGS = 5V VGS = 4V 50 Unless Otherwise Specified (Continued) 20 VGS = 10V 80s PULSE TEST VGS = 9V 1ms 1.0 OPERATION IN THIS AREA IS LIMITED BY rDS(ON) 10ms 100ms VDS , DRAIN TO SOURCE VOLTAGE (V) FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. OUTPUT CHARACTERISTICS 10 ID(ON), ON-STATE DRAIN CURRENT (A) 80s PULSE TEST VGS = 10V VGS = 8V VGS = 7V 20 VDS > ID(ON) x rDS(ON)MAX 80s PULSE TEST 16 25oC -55oC 125oC ID, DRAIN CURRENT (A) 8 VGS = 9V VGS = 6V 6 12 4 VGS = 5V 2 VGS = 4V 0 0 1 2 3 4 5 VDS, DRAIN TO SOURCE VOLTAGE (V) 8 4 0 0 2 4 6 8 VGS , GATE TO SOURCE VOLTAGE (V) 10 FIGURE 6. SATURATION CHARACTERISTICS FIGURE 7. TRANSFER CHARACTERISTICS 0.8 2s PULSE TEST NORMALIZED DRAIN TO SOURCE ON REISITANCE 2.50 VGS = 10V ID = 3A rDS(ON), DRAIN TO SOURCE ON RESISTANCE () 2.00 0.6 VGS = 10V 0.4 VGS = 20V 0.2 1.50 1.00 0.50 0 0 10 20 ID , DRAIN CURRENT (A) 30 40 0 -40 0 40 80 120 TJ , JUNCTION TEMPERATURE (oC) NOTE: Heating effect of 2s pulse is minimal. FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 4 IRFF120 Typical Performance Curves 1.25 ID = 250A NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE 1.15 C, CAPACITANCE (pF) 800 Unless Otherwise Specified (Continued) 1000 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS CDS + CGD 1.05 600 0.95 400 CISS COSS 0.85 200 CRSS 0.75 -40 0 40 80 120 TJ , JUNCTION TEMPERATURE (oC) 0 0 10 20 30 40 50 VDS , DRAIN TO SOURCE VOLTAGE (V) FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE 5 ISD, SOURCE TO DRAIN CURRENT (A) 80s PULSE TEST -55oC 25oC 100 5 gfs, TRANSCONDUCTANCE (S) 4 2 10 5 150oC 25oC 2 1.0 0 3 125oC 2 1 0 0 4 8 12 16 20 ID , DRAIN CURRENT (A) 1 2 3 VSD, SOURCE TO DRAIN VOLTAGE (V) FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE 20 ID = 6A VGS, GATE TO SOURCE (V) VDS = 50V 15 VDS = 20V 10 VDS = 80V 5 0 0 4 8 12 16 20 Qg(TOT) , TOTAL GATE CHARGE (nC) FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE 5 IRFF120 Test Circuits and Waveforms VDS tP L IAS VARY tP TO OBTAIN REQUIRED PEAK IAS RG + BVDSS VDS VDD DUT VGS 0V tP IAS 0.01 VDD 0 tAV FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORM tON td(ON) tr VDS RL 90% tOFF td(OFF) tf 90% + RG DUT - VDD 0 10% 90% 10% VGS 0 10% 50% PULSE WIDTH 50% VGS FIGURE 17. SWITCHING TIME TEST CIRCUIT FIGURE 18. RESISTIVE SWITCHING WAVEFORMS CURRENT REGULATOR VDS (ISOLATED SUPPLY) VDD Qg(TOT) VGS 12V BATTERY 0.2F 50k 0.3F SAME TYPE AS DUT Qgs Qgd D G DUT 0 VDS IG(REF) 0 IG CURRENT SAMPLING RESISTOR S VDS ID CURRENT SAMPLING RESISTOR IG(REF) 0 FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORMS 6 IRFF120 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 7 |
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